1. Field of the Invention
The present invention relates to a semiconductor device comprising a semiconductor chip on which an internal voltage generating circuit is provided, and more particularly to a semiconductor device comprising a reset signal generating circuit for generating a power-on-reset signal (hereinafter referred to as a POR signal) used for resetting an internal circuit thereof when a power source is turned ON or for keeping circuit operation halted until an internal potential is stabilized in order to prevent the unstable state from occurring when the power source is turned ON.
2. Description of the Background Art
In some cases, the semiconductor device has a structure in which the internal circuit is reset when the power source is turned ON or the circuit operation is kept halted until the internal potential is stabilized by using the POR signal in order to prevent the unstable state from occurring when the power source is turned ON.
FIG. 25 is a block diagram showing the structure of a semiconductor device which comprises a conventional POR signal generating circuit for generating a POR signal. In FIG. 25, reference numeral 1 designates a semiconductor chip, 2 designates a power input terminal provided on the semiconductor chip 1 for receiving an external voltage ExVdd given from the outside of the semiconductor chip 1, 3 designates an internal circuit provided in the semiconductor chip 1, 4 designates an internal voltage generating circuit for supplying an internal voltage intVdd to the internal circuit 3, and 5 designates a POR signal generating circuit for generating a POR signal to be sent to the internal circuit 3 based on the external voltage ExVdd.
FIG. 26 is a circuit diagram showing the structure of a POR circuit. In FIG. 26, reference numeral 6 designates an N channel MOS transistor having a gate to which the external voltage ExVdd is given, a drain to which the external voltage ExVdd is given, and a source, 7 designates a capacitor having a first end connected to the source of the transistor 6 and a second end connected to a ground potential point GND, 8 designates an N channel MOS transistor having a gate to which the external voltage ExVdd is given, a drain to which the external voltage ExVdd is given, and a source, 9 designates an N channel MOS transistor having a drain connected to the source of the transistor 8, a source connected to the ground potential point GND, and a gate connected to the first end of the capacitor 7, 10 designates an inverter having an input terminal connected to the drain of the transistor 9 and an output terminal for inverting and outputting the logic of a signal input to the input terminal, and 11 designates an inverter having an input terminal connected to the output terminal of the inverter 10 and an output terminal for inverting and outputting the logic of a signal input to the input terminal.
A pulse signal is output as the POR signal from the conventional POR signal generating circuit. The pulse width of the POR signal is determined by the charging time of the capacitor 7 because the conventional POR signal generating circuit has the above structure. However, the conventional POR signal generating circuit has problems that the POR signal is generated depending on the rise speed of an external power source before the internal voltage generating circuit fully operates and that the POR signal is generated by the change of the external voltage.
It is preferred that POR signals outputted on different timings are generated depending on a circuit structure in some cases, for example, in the case where a plurality of internal voltage generating circuits are provided on the semiconductor chip and the internal voltages have different generation timings. In the case of a DRAM, a plurality of potentials such as a substrate potential Vbb, a cell plate potential Vcp and the like are necessary. According to the semiconductor chip in which the external voltage ExVdd is dropped inside and the internal voltage intVdd is used, the cell plate potential Vcp is often generated by the internal voltage intVdd when the ground potential GND acts as a reference in consideration of the stability of the potential. A coupling capacity between a cell plate and a substrate is big. Consequently, the floating of the substrate potential Vbb may be caused by the coupling capacity when the cell plate potential Vcp rises. In order to prevent the floating, it is preferred that the substrate potential Vbb is kept fixed to the ground potential GND until the cell plate potential Vcp rises.
However, the POR signal generating circuit according to the prior art has the following problems. More specifically, the POR signal is generated by only the external voltage. For this reason, it is hard to generate signals which rise (or fall) at different timings, that is, at a comparatively early timing as the POR signal of the internal voltage generating circuit, and a signal which rises (or falls) after the cell plate potential Vcp is stabilized, that is, at a comparatively late timing as the POR signal of the internal voltage generating circuit used for setting the substrate potential Vbb.